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TAS5630B sles217d ? november 2010 ? revised march 2015 TAS5630B 300-w stereo and 400-w mono purepath ? hd analog-input power stage 1 features 3 description the TAS5630B device is a high-performance analog- 1 ? purepath ? hd enabled integrated feedback input class-d amplifier with integrated closed-loop provides: feedback technology (known as purepath hd ? signal bandwidth up to 80 khz for high- technology) with the ability to drive up to 300 w (1) frequency content from hd sources stereo into 4- ? to 8- ? speakers from a single 50-v supply. ? ultralow 0.03% thd at 1 w into 4 ? ? flat thd at all frequencies for natural sound purepath hd technology enables traditional ab- amplifier performance ( < 0.03% thd) levels while ? 80-db psrr (btl, no input signal) providing the power efficiency of traditional class-d ? > 100-db (a-weighted) snr amplifiers. ? click- and pop-free start-up unlike traditional class-d amplifiers, the distortion ? multiple configurations possible on the same curve does not increase until the output levels move pcb with stuffing options: into clipping. ? mono parallel bridge-tied load (pbtl) purepath hd technology enables lower idle losses, ? stereo bridge-tied load (btl) making the device even more efficient. when coupled with ti ? s class-g power-supply reference design for ? 2.1 single-ended stereo pair and btl tas563x, industry-leading levels of efficiency can be subwoofer achieved. ? quad single-ended outputs ? total output power at 10% thd+n device information (1) ? 400 w in mono pbtl configuration part number package body size (nom) ? 300 w per channel in stereo btl hssop (44) 15.90 mm 11.00 mm TAS5630B configuration htqfp (64) 14.00 mm 14.00 mm ? 145 w per channel in quad single-ended (1) for all available packages, see the orderable addendum at configuration the end of the data sheet. ? high-efficiency power stage ( > 88%) with 60-m ? typical TAS5630B application block diagram output mosfets ? two thermally enhanced package options: ? phd (64-pin qfp) ? dkd (44-pin psop3) ? self-protection design (including undervoltage, overtemperature, clipping, and short-circuit protection) with error reporting ? emi compliant when used with recommended system design 2 applications ? mini combo system ? av receivers (1) achievable output power levels are dependent on the thermal configuration of the target application. a high-performance ? dvd receivers thermal interface material between the exposed package heat slug and the heat sink should be used to achieve high output ? active speakers power levels. 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. purepath tm hd class-g power supply ref. design 110 vac 240 vac ? 25 vC50 v analog audio input 12 v purepath tm hd TAS5630B (2.1 configuration) ! ? ! ? ! ? 3 opa1632 15 v productfolder sample &buy technical documents tools & software support &community
TAS5630B sles217d ? november 2010 ? revised march 2015 www.ti.com table of contents 7.1 overview ................................................................. 14 1 features .................................................................. 1 7.2 functional block diagram ....................................... 14 2 applications ........................................................... 1 7.3 feature description ................................................. 15 3 description ............................................................. 1 7.4 device functional modes ........................................ 18 4 revision history ..................................................... 2 8 application and implementation ........................ 19 5 pin configuration and functions ......................... 4 8.1 application information ............................................ 19 6 specifications ......................................................... 7 8.2 typical application .................................................. 20 6.1 absolute maximum ratings ...................................... 7 9 power supply recommendations ...................... 27 6.2 esd ratings .............................................................. 7 10 layout ................................................................... 27 6.3 recommended operating conditions ....................... 7 10.1 layout guidelines ................................................. 27 6.4 thermal information .................................................. 8 10.2 layout example .................................................... 28 6.5 electrical characteristics ........................................... 8 11 device and documentation support ................. 30 6.6 audio characteristics (btl) .................................... 10 11.1 trademarks ........................................................... 30 6.7 audio specification (single-ended output) ............ 10 11.2 electrostatic discharge caution ............................ 30 6.8 audio specification (pbtl) .................................... 11 11.3 glossary ................................................................ 30 6.9 typical characteristics ............................................ 11 12 mechanical, packaging, and orderable 7 detailed description ............................................ 14 information ........................................................... 30 4 revision history changes from revision c (september 2012) to revision d page ? added pin configuration and functions section, esd ratings table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section .............................. 1 ? changed thermal information table data. .............................................................................................................................. 8 changes from revision b (november 2011) to revision c page ? changed analog comparator reference node, vi_cm vlaues from: min = 1.5 typ = 1.75 max = 1.9 to: min = 1.75 typ = 2 max = 2.15 ...................................................................................................................................................... 8 ? changed analog inputs - v in typ value from 3.5 to 5 v pp ............................................................................................ 8 ? changed the v ih and v il test conditions from: input_x, m1, m2, m3, reset to: m1, m2, m3, reset ........................ 9 ? deleted - r l = 2 ? , 1% thd+n, unclipped output signal from p o in the audio specification (pbtl) table ....................... 11 changes from revision a (november 2011) to revision b page ? changed the r int_pu parameters from /otw1 to vreg, /otw2 to vreg, /sd to vreg to /otw, /otw1, /otw2, /clip, ready, /sd to vre .................................................................................................................................................... 9 ? added text to the phd package section. ............................................................................................................................. 17 ? added text to the dkd package section .............................................................................................................................. 17 changes from original (november 2010) to revision a page ? changed title from: 600-w mono to: 400-w mono ......................................................................................................... 1 ? changed feature from: 600 w per channel in mono pbtl configuration to: 400 w per channel in mono pbtl configuration .......................................................................................................................................................................... 1 ? changed the pin one location package image .................................................................................................................... 5 ? changed r l (pbtl) load impedance min value from: 1.6 to: 2.4 , and typ value from 2 to: 3 ............................. 7 ? added footnotes to the roc table ......................................................................................................................................... 7 ? added r ocp information to the roc table ............................................................................................................................ 8 2 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: TAS5630B
TAS5630B www.ti.com sles217d ? november 2010 ? revised march 2015 ? changed the i oc typical value from: 19 a to: 15 a ............................................................................................................. 9 ? deleted - r l = 2 ? , 10%, thd+n, clipped input signal from p o in the audio specification (pbtl) table .......................... 11 ? replaced the typical characteristics, pbtl configuration graphs ............................................................... 12 ? added section - click and pop in se-mode ......................................................................................................................... 18 ? added section - pbtl overload and short circuit ............................................................................................................... 18 ? replaced the package heat dissipation ratings table with the thermal information table ....................... 18 copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: TAS5630B
TAS5630B sles217d ? november 2010 ? revised march 2015 www.ti.com 5 pin configuration and functions dkd package 44 pins hssop top view phd package 64 pins htqfp top view 4 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: TAS5630B 26 16 15 oc_adj 14 reset 13 c_startup 12 input_a 11 input_b 10 vi_cm 9 gnd 8 agnd 7 vreg 6 input_c 5 input_d 4 freq_adj 3 osc_io+ 2 osc_io- 1 sd 64-pins qfp package 32 gnd_d 31 pvdd_d 30 pvdd_d 29 out_d 28 out_d 27 bst_d gvdd_d 25 gvdd_c 24 gnd 23 gnd 22 nc 21 nc 20 nc 19 nc 18 psu_ref 17 vdd 33 gnd_d 34 gnd_c 35 gnd_c 36 out_c 37 out_c 38 pvdd_c 39 pvdd_c 40 bst_c 41 bst_b 42 pvdd_b 43 out_b 44 gnd_b 45 gnd_a 46 47 48 55 49 50 51 ready 52 m1 53 m2 54 m3 gnd 56 gnd 57 gvdd_b 58 gvdd_a 59 bst_a 60 out_a 61 out_a 62 pvdd_a 63 pvdd_a 64 gnd_a otw1 clip pvdd_b out_b gnd_b otw2 44 pins package (top view) 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 4443 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 m3 oc_adj vdd psu_ref m2 m1 ready otw sd osc_io- osc_io+ freq_adj input_d input_c vreg agnd gnd vi_cm input_b input_a c_startup reset gnd_c out_a bst_a out_b bst_b pvdd_b pvdd_a bst_c pvdd_c out_c gnd_a gnd_b out_d pvdd_d bst_d gnd_d gvdd_ab gvdd_cd pvdd_a pvdd_d out_d out_a
TAS5630B www.ti.com sles217d ? november 2010 ? revised march 2015 figure 1. pin one location phd package pin functions pin function (1) description name htqfp hssop agnd 8 10 p analog ground bst_a 54 43 p hs bootstrap supply (bst), external 0.033- f capacitor to out_a required. bst_b 41 34 p hs bootstrap supply (bst), external 0.033- f capacitor to out_b required. bst_c 40 33 p hs bootstrap supply (bst), external 0.033- f capacitor to out_c required. bst_d 27 24 p hs bootstrap supply (bst), external 0.033- f capacitor to out_d required. clip 18 ? o clipping warning; open drain; active-low c_startup 3 5 o start-up ramp requires a charging capacitor of 4.7 nf to agnd in btl mode freq_adj 12 14 i pwm frame-rate-programming pin requires resistor to agnd 7, 23, 24, 57, gnd 9 p ground 58 gnd_a 48, 49 38 p power ground for half-bridge a gnd_b 46, 47 37 p power ground for half-bridge b gnd_c 34, 35 30 p power ground for half-bridge c gnd_d 32, 33 29 p power ground for half-bridge d gvdd_a 55 ? p gate-drive voltage supply requires 0.1- f capacitor to gnd_a gvdd_b 56 ? p gate drive voltage supply requires 0.1- f capacitor to gnd_b gvdd_c 25 ? p gate drive voltage supply requires 0.1- f capacitor to gnd_c gvdd_d 26 ? p gate drive voltage supply requires 0.1- f capacitor to gnd_d gvdd_ab ? 44 p gate drive voltage supply requires 0.22- f capacitor to gnd_a/gnd_b gvdd_cd ? 23 p gate drive voltage supply requires 0.22- f capacitor to gnd_c/gnd_d input_a 4 6 i input signal for half-bridge a input_b 5 7 i input signal for half-bridge b input_c 10 12 i input signal for half-bridge c input_d 11 13 i input signal for half-bridge d m1 20 20 i mode selection m2 21 21 i mode selection m3 22 22 i mode selection nc 59 ? 62 ? ? no connect; pins may be grounded. (1) i = input, o = output, p = power copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: TAS5630B pin 1 markerwhite dot electrical pin 1
TAS5630B sles217d ? november 2010 ? revised march 2015 www.ti.com pin functions (continued) pin function (1) description name htqfp hssop analog overcurrent-programming pin requires resistor to agnd. 64-pin oc_adj 1 3 o package (phd) = 22 k . 44-pin psop3 (dkd) = 24 k osc_io+ 13 15 i/o oscillator master/slave output/input osc_io ? 14 16 i/o oscillator master/slave output/input otw ? 18 o overtemperature warning signal, open-drain, active-low otw1 16 ? o overtemperature warning signal, open-drain, active-low otw2 17 ? o overtemperature warning signal, open-drain, active-low out_a 52, 53 39, 40 o output, half-bridge a out_b 44, 45 36 o output, half-bridge b out_c 36, 37 31 o output, half-bridge c out_d 28, 29 27, 28 o output, half-bridge d psu_ref 63 1 p psu reference requires close decoupling of 330 pf to agnd. power-supply input for half-bridge a requires close decoupling of 0.01- f pvdd_a 50, 51 41, 42 p capacitor in parallel with 2.2- f capacitor to gnd_a. power-supply input for half-bridge b requires close decoupling of 0.01- f pvdd_b 42, 43 35 p capacitor in parallel with 2.2- f capacitor to gnd_b. power-supply input for half-bridge c requires close decoupling of 0.0- f pvdd_c 38, 39 32 p capacitor in parallel with 2.2- f capacitor to gnd_c. power-supply input for half-bridge d requires close decoupling of 0.01- f pvdd_d 30, 31 25, 26 p capacitor in parallel with 2.2- f capacitor to gnd_d. ready 19 19 o normal operation; open-drain; active-high reset 2 4 i device reset input; active-low sd 15 17 o shutdown signal, open-drain, active-low power supply for digital voltage regulator requires a 10- f capacitor in parallel vdd 64 2 p with a 0.1- f capacitor to gnd for decoupling. analog comparator reference node requires close decoupling of 1 nf to vi_cm 6 8 o agnd. vreg 9 11 p regulator supply filter pin requires 0.1- f capacitor to agnd. 6 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: TAS5630B
TAS5630B www.ti.com sles217d ? november 2010 ? revised march 2015 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range unless otherwise noted (1) min max unit vdd to agnd ? 0.3 13.2 v gvdd to agnd ? 0.3 13.2 v pvdd_x to gnd_x (2) ? 0.3 69 v out_x to gnd_x (2) ? 0.3 69 v bst_x to gnd_x (2) ? 0.3 82.2 v bst_x to gvdd_x (2) ? 0.3 69 v vreg to agnd ? 0.3 4.2 v gnd_x to gnd ? 0.3 0.3 v gnd_x to agnd ? 0.3 0.3 v oc_adj, m1, m2, m3, osc_io+, osc_io ? , freq_adj, vi_cm, c_startup, psu_ref to agnd ? 0.3 4.2 v input_x ? 0.3 7 v reset, sd, otw1, otw2, clip, ready to agnd ? 0.3 7 v continuous sink current ( sd, otw1, otw2, clip, ready) 9 ma operating junction temperature, t j 0 150 c storage temperature, t stg ? 40 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) these voltages represents the dc voltage + peak ac waveform measured at the terminal of the device in all conditions. 6.2 esd ratings value unit human body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v (esd) electrostatic discharge v charged-device model (cdm), per jedec specification jesd22- 500 c101 (2) (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit pvdd_x half-bridge supply dc supply voltage 25 50 52.5 v gvdd_x supply for logic regulators and gate-drive circuitry dc supply voltage 10.8 12 13.2 v vdd digital regulator supply voltage dc supply voltage 10.8 12 13.2 v r l (btl) 3.5 4 output filter according to schematics in the r l (se) (2) load impedance (1) 1.8 2 ? application information section r l (pbtl) (2) 2.4 3 l output (btl) 7 10 l output (se) (2) output filter inductance (1) minimum output inductance at i oc 7 15 h l output (pbtl) (2) 7 10 nominal 385 400 415 pwm frame rate selectable for am interference f pwm am1 315 333 350 khz avoidance; 1% resistor tolerance. am2 260 300 335 nominal; master mode 9.9 10 10.1 r freq_adj pwm frame-rate-programming resistor am1; master mode 19.8 20 20.2 k ? am2; master mode 29.7 30 30.3 (1) values are for actual measured impedance over all combinations of tolerance, current and temperature and not simply the component rating. (2) see additional details for se and pbtl in system design considerations . copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: TAS5630B
TAS5630B sles217d ? november 2010 ? revised march 2015 www.ti.com recommended operating conditions (continued) over operating free-air temperature range (unless otherwise noted) min nom max unit voltage on freq_adj pin for slave mode v freq_adj slave mode 3.3 v operation 64-pin qfp package (phd) 22 33 overcurrent-protection-programming resistor, cycle-by-cycle mode 44-pin psop3 package (dkd) 24 33 r ocp k overcurrent-protection-programming resistor, phd or dkd 47 68 latching mode t j junction temperature 0 125 c 6.4 thermal information TAS5630B thermal metric (1) phd (htqfp) dkd (hssop) unit 64 pins 44 pins r ja junction-to-ambient thermal resistance 8.6 8.8 r jc(top) junction-to-case (top) thermal resistance 0.3 0.4 r jb junction-to-board thermal resistance 2.1 3.0 c/w jt junction-to-top characterization parameter 0.4 0.4 jb junction-to-board characterization parameter 2.1 3.0 (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report ( spra953 ). 6.5 electrical characteristics pvdd_x = 50 v, gvdd_x = 12 v, vdd = 12 v, t c (case temperature) = 75 c, f s = 400 khz, unless otherwise specified. parameter test conditions min typ max unit internal voltage regulator and current consumption voltage regulator, only used as reference vreg vdd = 12 v 3 3.3 3.6 v node, vreg vi_cm analog comparator reference node, vi_cm 1.75 2 2.15 v operating, 50% duty cycle 22.5 i vdd vdd supply current ma idle, reset mode 22.5 50% duty cycle 12.5 i gvdd_x gvdd_x gate-supply current per half-bridge ma reset mode 1.5 50% duty cycle with recommended output 13.3 ma filter i pvdd_x half-bridge supply current reset mode, no switching 870 a analog inputs r in input resistance ready = high 33 k ? maximum input voltage with symmetrical v in 5 v pp output swing i in maximum input current 342 a g voltage gain (v out /v in ) 23 db oscillator nominal, master mode 3.85 4 4.15 f osc_io+ am1, master mode f pwm 10 3.15 3.33 3.5 mhz am2, master mode 2.6 3 3.35 v ih high level input voltage 1.86 v v il low level input voltage 1.45 v 8 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: TAS5630B
TAS5630B www.ti.com sles217d ? november 2010 ? revised march 2015 electrical characteristics (continued) pvdd_x = 50 v, gvdd_x = 12 v, vdd = 12 v, t c (case temperature) = 75 c, f s = 400 khz, unless otherwise specified. parameter test conditions min typ max unit output-stage mosfets drain-to-source resistance, low side (ls) 60 100 t j = 25 c, excludes metallization r ds(on) m ? resistance, gvdd = 12 v drain-to-source resistance, high side (hs) 60 100 i/o protection undervoltage protection limit, gvdd_x and v uvp,g 9.5 v vdd v uvp,hyst (1) 0.6 v otw1 (1) overtemperature warning 1 95 100 105 c otw2 (1) overtemperature warning 2 115 125 135 c temperature drop needed below otw otw hyst (1) temperature for otw to be inactive after 25 c otw event overtemperature error 145 155 165 c ote (1) ote-otw differential 30 c a reset must occur for sd to be released ote hyst (1) 25 following an ote event. olpc overload protection counter f pwm = 400 khz 2.6 ms resistor ? programmable, nominal peak current in 1- ? load, 15 64-pin qfp package (phd) r ocp = 22 k ? overcurrent limit protection resistor ? programmable, nominal peak i oc current in 1- ? load, a 15 44-pin psop3 package (dkd), r ocp = 24 k ? resistor ? programmable, nominal peak current in 1- ? load, overcurrent limit protection, latched 15 r ocp = 47 k ? time from switching transition to flip-state i oct overcurrent response time 150 ns induced by overcurrent connected when reset is active to internal pulldown resistor at output of each i pd provide bootstrap charge. not used in se 3 ma half-bridge mode static digital specifications v ih high-level input voltage 2 v m1, m2, m3, reset v il low-level input voltage 0.8 v i lkg input leakage current 100 a otw/shutdown (sd) internal pullup resistance, otw, otw1, r int_pu 20 26 32 k ? otw2, clip, ready, sd to vreg internal pullup resistor 3 3.3 3.6 v oh high-level output voltage v external pullup of 4.7 k ? to 5 v 4.5 5 v ol low-level output voltage i o = 4 ma 200 500 mv device fanout otw, otw1, otw2, sd, fanout no external pullup 30 devices clip, ready (1) specified by design. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: TAS5630B
TAS5630B sles217d ? november 2010 ? revised march 2015 www.ti.com 6.6 audio characteristics (btl) pcb and system configuration are in accordance with recommended guidelines. audio frequency = 1 khz, pvdd_x = 50 v, gvdd_x = 12 v, r l = 4 ? , f s = 400 khz, r oc = 22 k ? , t c = 75 c; output filter: l dem = 7 h, c dem = 680 nf, mode = 010, unless otherwise noted. parameter test conditions min typ max unit r l = 4 ? , 10% thd+n, clipped output signal 300 r l = 6 ? , 10% thd+n, clipped output signal 210 r l = 8 ? , 10% thd+n, clipped output signal 160 p o power output per channel w r l = 4 ? , 1% thd+n, unclipped output signal 240 r l = 6 ? , 1% thd+n, unclipped output signal 160 r l = 8 ? , 1% thd+n, unclipped output signal 125 thd+n total harmonic distortion + noise 1 w 0.03% a-weighted, aes17 filter, input capacitor v n output integrated noise 270 v grounded |v os | output offset voltage inputs ac-coupled to agnd 20 50 mv snr signal-to-noise ratio (1) a-weighted, aes17 filter 100 db dnr dynamic range a-weighted, aes17 filter 100 db p idle power dissipation due to idle losses (i pvdd_x ) p o = 0, four channels switching (2) 2.7 w (1) snr is calculated relative to 1% thd+n output level. (2) actual system idle losses also are affected by core losses of output inductors. 6.7 audio specification (single-ended output) pcb and system configuration are in accordance with recommended guidelines. audio frequency = 1khz, pvdd_x = 50 v, gvdd_x = 12 v, r l = 4 ? , f s = 400 khz, r oc = 22 k ? , t c = 75 c; output filter: l dem = 15 h, c dem = 470 f, mode = 100, unless otherwise noted. parameter test conditions min typ max unit r l = 2 ? , 10% thd+n, clipped output signal 145 r l = 3 ? , 10% thd+n, clipped output signal 100 r l = 4 ? , 10% thd+n, clipped output signal 75 p o power output per channel w r l = 2 ? , 1% thd+n, unclipped output signal 110 r l = 3 ? , 1% thd+n, unclipped output signal 75 r l = 4 ? , 1% thd+n, unclipped output signal 55 thd+n total harmonic distortion + noise 1 w 0.07% v n output integrated noise a-weighted, aes17 filter, input capacitor grounded 340 v snr signal-to-noise ratio (1) a-weighted, aes17 filter 93 db dnr dynamic range a-weighted, aes17 filter 93 db power dissipation due to idle losses p idle p o = 0, four channels switching (2) 2 w (i pvdd_x ) (1) snr is calculated relative to 1% thd+n output level. (2) actual system idle losses are affected by core losses of output inductors. 10 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: TAS5630B
TAS5630B www.ti.com sles217d ? november 2010 ? revised march 2015 6.8 audio specification (pbtl) pcb and system configuration are in accordance with recommended guidelines. audio frequency = 1 khz, pvdd_x = 50 v, gvdd_x = 12 v, r l = 3 ? , f s = 400 khz, r oc = 22 k ? , t c = 75 c; output filter: l dem = 7 h, c dem = 1.5 f, mode = 101-10, unless otherwise noted. parameter test conditions min typ max unit r l = 3 ? , 10% thd+n, clipped output signal 400 r l = 4 ? , 10% thd+n, clipped output signal 300 p o power output per channel w r l = 3 ? , 1% thd+n, unclipped output signal 310 r l = 4 ? , 1% thd+n, unclipped output signal 230 thd+n total harmonic distortion + noise 1 w 0.05% v n output integrated noise a-weighted 260 v snr signal to noise ratio (1) a-weighted 100 db dnr dynamic range a-weighted 100 db p idle power dissipation due to idle losses (ipvdd_x) p o = 0, four channels switching (2) 2.7 w (1) snr is calculated relative to 1% thd-n output level. (2) actual system idle losses are affected by core losses of output inductors. 6.9 typical characteristics 6.9.1 btl configuration figure 2. total harmonic + noise vs output power figure 3. output power vs supply voltage figure 4. unclipped output power vs supply voltage figure 5. system efficiency vs output power copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: TAS5630B 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0 100 200 300 400 500 600 700 2 channel output power ? w efficiency ? % 4 w 6 w 8 w t c = 25 c thd+n at 10% g001 0.005 0.01 0.1 1 10 20m 100m 1 10 100 400 p o ? output power ? w thd+n ? total harmonic distortion + noise ? % 4 w 6 w 8 w t c = 75 c g001 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 25 30 35 40 45 50 pvdd ? supply voltage ? v p o ? output power ? w 4 w 6 w 8 w t c = 75 c thd+n at 10% g001 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 25 30 35 40 45 50 pvdd ? supply voltage ? v p o ? output power ? w 4 w 6 w 8 w t c = 75 c g001
TAS5630B sles217d ? november 2010 ? revised march 2015 www.ti.com btl configuration (continued) figure 6. system power loss vs output power figure 7. output power vs case temperature figure 8. noise amplitude vs frequency 6.9.2 se configuration 1 channel driven figure 9. total harmonic distortion + noise vs output figure 10. output power vs supply voltage power 12 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: TAS5630B 0.005 0.01 0.1 1 10 20m 100m 1 10 100 200 p o ? output power ? w thd+n ? total harmonic distortion + noise ? % 2 w 3 w 4 w t c = 75 c g001 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 25 30 35 40 45 50 pvdd ? supply voltage ? v p o ? output power ? w 2 w 3 w 4 w t c = 75 c thd+n at 10% g001 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k f ? frequency ? hz noise amplitude ? db 4 w t c = 75 c v ref = 35.36 v sample rate = 48khzfft size = 16384 g001 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0 100 200 300 400 500 600 700 2 channel output power ? w power loss ? w 4 w 6 w 8 w t c = 25 c thd+n at 10% g001 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 ?10 0 10 20 30 40 50 60 70 80 90 100 110 t c ? case temperature ? c p o ? output power ? w 4 w 6 w 8 w thd+n at 10% g001
TAS5630B www.ti.com sles217d ? november 2010 ? revised march 2015 se configuration (continued) figure 11. output power vs case temperature 6.9.3 pbtl configuration figure 12. total harmonic distortion + noise vs output figure 13. output power vs supply voltage power figure 14. output power vs case temperature copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 13 product folder links: TAS5630B 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 ?10 0 10 20 30 40 50 60 70 80 90 100 110 t c ? case temperature ? c p o ? output power ? w 2 w 3 w 4 w thd+n at 10% g001 0 50 100 150 200 250 300 350 400 450 500 ?10 0 10 20 30 40 50 60 70 80 90 100 110 t c ? case temperature ? c p o ? output power ? w 3 w 4 w 6 w 8 w thd+n at 10% g001 0.005 0.01 0.1 1 10 20m 100m 1 10 100 700 p o ? output power ? w thd+n ? total harmonic distortion + noise ? % 3 w 4 w 6 w 8 w t c = 75 c g001 0 50 100 150 200 250 300 350 400 450 500 25 30 35 40 45 50 pvdd ? supply voltage ? v p o ? output power ? w 3 w 4 w 6 w 8 w t c = 75 c thd+n at 10% g001
TAS5630B sles217d ? november 2010 ? revised march 2015 www.ti.com 7 detailed description 7.1 overview TAS5630B is an analog input, audio pwm (class-d) amplifier. the output of the TAS5630B can be configured for single-ended, bridge-tied load (btl) or parallel btl (pbtl) output. it requires two rails for power supply, pvdd and 12 v (gvdd and vdd). the following functional block diagram shows interconnections of internal supplies, control logic, gate drives and power amplifiers. detailed schematic can be viewed in TAS5630B evm user's guide ( slau287 ). 7.2 functional block diagram 14 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: TAS5630B m1 m2 /reset /sd /otw2 agnd oc_adj vreg vdd gvdd_a m3 gnd input_d out_a gnd_a pvdd_a bst_a gvdd_a pwm activity detector gvdd _c gvdd_b input_c out_b gnd_b pvdd_b bst_b gvdd_b gvdd_d gvdd_c out_c gnd_c pvdd_c bst_c gvdd_d out_d gnd_d pvdd_d bst_d input_b input_a pvdd_x out_x gnd_x timing control control gate-drive timing control control gate-drive timing control control gate-drive timing control control gate-drive pwm receiver pwm receiver pwm receiver pwm receiver + - analog comparator mux + - + - + - protection & i/o logic vi_cm startup control power-up reset temp sense over-load protection ppsc cb3c uvp current sense vreg c_startup analog loop filter analog loop filter analog loop filter analog loop filter oscillator freq_adj osc_sync_io- analog input mux psu_ff psu_ref 44 4 pvdd_x 4 gnd osc_sync_io+ /otw1 ready /clip
TAS5630B www.ti.com sles217d ? november 2010 ? revised march 2015 7.3 feature description 7.3.1 power supplies to facilitate system design, the TAS5630B needs only a 12-v supply in addition to the (typical) 50-v power-stage supply. an internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. additionally, all circuitry requiring a floating voltage supply, for example, the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge. to provide outstanding electrical and acoustical characteristics, the pwm signal path, including gate drive and output stage, is designed as identical, independent half-bridges. for this reason, each half-bridge has separate gate drive supply pins (gvdd_x), bootstrap pins (bst_x), and power-stage supply pins (pvdd_x). furthermore, an additional pin (vdd) is provided as supply for all common circuits. although supplied from the same 12-v source, it is highly recommended to separate gvdd_a, gvdd_b, gvdd_c, gvdd_d, and vdd on the printed-circuit board (pcb) by rc filters (see typical application for details). these rc filters provide the recommended high-frequency isolation. special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. in general, inductance between the power supply pins and decoupling capacitors must be avoided. (see slau287 for additional information.) for a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (bst_x) to the power-stage output pin (out_x). when the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (gvdd_x) and the bootstrap pin. when the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. in an application with pwm switching frequencies in the range from 300 khz to 400 khz, it is recommended to use 33-nf ceramic capacitors, size 0603 or 0805, for the bootstrap supply. these 33-nf capacitors ensure sufficient energy storage, even during minimal pwm duty cycles, to keep the high-side power stage fet (ldmos) fully turned on during the remaining part of the pwm cycle. special attention should be paid to the power-stage power supply; this includes component selection, pcb placement, and routing. as indicated, each half-bridge has independent power-stage supply pins (pvdd_x). for optimal electrical performance, emi compliance, and system reliability, it is important that each pvdd_x pin is decoupled with a 2.2- f ceramic capacitor placed as close as possible to each supply pin. it is recommended to follow the pcb layout of the TAS5630B reference design. for additional information on recommended power supply and required components, see typical application . the 12-v supply should be from a low-noise, low-output-impedance voltage regulator. likewise, the 50-v power- stage supply is assumed to have low output impedance and low noise. the power-supply sequence is not critical as facilitated by the internal power-on-reset circuit. moreover, the TAS5630B is fully protected against erroneous power-stage turnon due to parasitic gate charging. thus, voltage-supply ramp rates (dv/dt) are non-critical within the specified range (see recommended operating conditions ). 7.3.2 system power-up and power-down sequence 7.3.2.1 powering up the TAS5630B does not require a power-up sequence. the outputs of the h-bridges remain in a high- impedance state until the gate-drive supply voltage (gvdd_x) and vdd voltage are above the undervoltage protection (uvp) voltage threshold (see electrical characteristics ). although not specifically required, it is recommended to hold reset in a low state while powering up the device. this allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output. 7.3.2.2 powering down the TAS5630B does not require a power-down sequence. the device remains fully operational as long as the gate-drive supply (gvdd_x) voltage and vdd voltage are above the undervoltage protection (uvp) voltage threshold (see electrical characteristics ). although not specifically required, it is a good practice to hold reset low during power down, thus preventing audible artifacts including pops or clicks. 7.3.3 error reporting the sd, otw, otw1, and otw2 pins are active-low, open-drain outputs. their function is for protection-mode signaling to a pwm controller or other system-control device. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 15 product folder links: TAS5630B
TAS5630B sles217d ? november 2010 ? revised march 2015 www.ti.com feature description (continued) any fault resulting in device shutdown is signaled by the sd pin going low. likewise, otw and otw2 go low when the device junction temperature exceeds 125 c and otw1 goes low when the junction temperature exceeds 100 c (see table 1 ). table 1. error reporting otw2, sd otw1 description otw 0 0 0 overtemperature (ote) or overload (olp) or undervoltage (uvp) overload (olp) or undervoltage (uvp). junction temperature higher than 100 c (overtemperature 0 0 1 warning) 0 1 1 overload (olp) or undervoltage (uvp) 1 0 0 junction temperature higher than 125 c (overtemperature warning) 1 0 1 junction temperature higher than 100 c (overtemperature warning) 1 1 1 junction temperature lower than 100 c and no olp or uvp faults (normal operation) note that asserting either reset low forces the sd signal high, independent of faults being present. ti recommends monitoring the otw signal using the system microcontroller and responding to an overtemperature warning signal by, for example, turning down the volume to prevent further heating of the device resulting in device shutdown (ote). to reduce external component count, an internal pullup resistor to 3.3 v is provided on both sd and otw outputs. level compliance for 5-v logic can be obtained by adding external pullup resistors to 5 v (see electrical characteristics for further specifications). 7.3.4 device protection system the TAS5630B contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overload, overtemperature, and undervoltage. the TAS5630B responds to a fault by immediately setting the power stage in a high-impedance (hi-z) state and asserting the sd pin low. in situations other than overload and overtemperature error (ote), the device automatically recovers when the fault condition has been removed, that is, the supply voltage has increased. the device functions on errors, as shown in the following table. table 2. device protection system btl mode pbtl mode se mode local error in turns off or in local error in turns off or in local error in turns off or in a a a a + b a + b b b b a + b + c + d c c c c + d c + d d d d bootstrap uvp does not shut down according to the table; it shuts down the respective half-bridge. 16 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: TAS5630B
TAS5630B www.ti.com sles217d ? november 2010 ? revised march 2015 7.3.5 pin-to-pin short-circuit protection (ppsc) the ppsc detection system protects the device from permanent damage if a power output pin (out_x) is shorted to gnd_x or pvdd_x. for comparison, the oc protection system detects an overcurrent after the demodulation filter, whereas ppsc detects shorts directly at the pin before the filter. ppsc detection is performed at startup, that is, when vdd is supplied; consequently, a short to either gnd_x or pvdd_x after system startup does not activate the ppsc detection system. when ppsc detection is activated by a short on the output, all half-bridges are kept in a hi-z state until the short is removed; the device then continues the startup sequence and starts switching. the detection is controlled globally by a two-step sequence. the first step ensures that there are no shorts from out_x to gnd_x; the second step tests that there are no shorts from out_x to pvdd_x. the total duration of this process is roughly proportional to the capacitance of the output lc filter. the typical duration is < 15 ms/ f. while the ppsc detection is in progress, sd is kept low, and the device does not react to changes applied to the reset pins. if no shorts are present the ppsc detection passes, and sd is released, a device reset does not start a new ppsc detection. ppsc detection is enabled in btl and pbtl output configurations; the detection is not performed in se mode. to make sure the ppsc detection system is not tripped, it is recommended not to insert resistive load between out_x and gnd_x or pvdd_x. 7.3.6 overtemperature protection the two different package options have individual overtemperature protection schemes. phd package: the TAS5630B phd package option has a three-level temperature-protection system that asserts an active-low warning signal ( otw1) when the device junction temperature exceeds 100 c (typical), ( otw2) when the device junction temperature exceeds 125 c (typical) and, if the device junction temperature exceeds 155 c (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (hi-z) state and sd being asserted low. ote is latched in this case. to clear the ote latch, reset must be asserted. thereafter, the device resumes normal operation. for highest reliability, the reset should not be asserted until otw1 has cleared. dkd package: the TAS5630B dkd package option has a two-level temperature-protection system that asserts an active-low warning signal ( otw) when the device junction temperature exceeds 125 c (typical) and, if the device junction temperature exceeds 155 c (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (hi-z) state and sd being asserted low. ote is latched in this case. to clear the ote latch, reset must be asserted. it is recommended to wait until otw has cleared before asserting reset. thereafter, the device resumes normal operation. 7.3.7 undervoltage protection (uvp) and power-on reset (por) the uvp and por circuits of the TAS5630B fully protect the device in any power-up/down and brownout situation. while powering up, the por circuit resets the overload circuit (olp) and ensures that all circuits are fully operational when the gvdd_x and vdd supply voltages reach the levels stated in electrical characteristics . although gvdd_x and vdd are independently monitored, a supply voltage drop below the uvp threshold on any vdd or gvdd_x pin results in all half-bridge outputs immediately being set in the high- impedance (hi-z) state and sd being asserted low. the device automatically resumes operation when all supply voltages have increased above the uvp threshold. 7.3.8 device reset when reset is asserted low, all power-stage fets in the four half-bridges are forced into a high-impedance (hi-z) state. in btl modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables weak pulldown of the half-bridge outputs. in the se mode, the output is forced into a high-impedance state when asserting the reset input low. asserting reset input low removes any fault information to be signaled on the sd output; that is, sd is forced high. a rising-edge transition on reset input allows the device to resume operation after an overload fault. to ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of sd. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 17 product folder links: TAS5630B
TAS5630B sles217d ? november 2010 ? revised march 2015 www.ti.com 7.3.9 click and pop in se-mode the btl startup has low click and pop due to the trimmed output dc offset, see audio characteristics (btl) . the startup of the btl+2 x se system ( figure 21 ) or 4xse ( figure 20 ) is more difficult to get click and pop free, than the pure btl solution; therefore, evaluating the resulting click and pop before designing in the device is recommended. 7.3.10 pbtl overload and short circuit the TAS5630B has extensive overload and short circuit protection. in btl and se mode, it is fully protected against speaker terminal overloads, terminal-to-terminal short circuit, and short circuit to gnd or pvdd. the protection works by limiting the current, by flipping the state of the output mosfets; thereby, ramping currents down in the inductor. this only works when the inductor is not saturated, the recommended minimum inductor values are listed in recommended operating conditions . in btl mode, the short circuit currents can reach more than 15 a, so when connecting the device in pbtl mode (mono), the currents double ? that is more than 30 a, and with these high currents, the protection system will limit pbtl speaker overloads, terminal-to-terminal shorts, and terminal-to-gnd shorts. pbtl mode short circuit to pvdd is not recommended. 7.3.11 oscillator the oscillator frequency can be trimmed by external control of the freq_adj pin. to reduce interference problems while using a radio receiver tuned within the am band, the switching frequency can be changed from nominal to lower values. these values should be chosen such that the nominal and the lower-value switching frequencies together result in the fewest cases of interference throughout the am band, and can be selected by the value of the freq_adj resistor connected to agnd in master mode. for slave-mode operation, turn off the oscillator by pulling the freq_adj pin to vreg. this configures the osc_i/o pins as inputs, which must be slaved from an external clock. 7.4 device functional modes table 3. mode selection pins mode pins output analog input description configuration m3 m2 m1 0 0 0 differential 2 btl ad mode 0 0 1 ? ? reserved 0 1 0 differential 2 btl bd mode differential single- 0 1 1 1 btl +2 se bd mode, btl differential ended 1 0 0 single-ended 4 se ad mode input_c (1) input_d (1) 1 0 1 differential 1 pbtl 0 0 ad mode 1 0 bd mode 1 1 0 reserved 1 1 1 (1) input_c and d are used to select between a subset of ad and bd mode operations in pbtl mode (1=vreg and 0=agnd). 18 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: TAS5630B
TAS5630B www.ti.com sles217d ? november 2010 ? revised march 2015 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information 8.1.1 pcb material recommendation ti recommends fr-4 2-oz. (70- m) glass epoxy material for use with the TAS5630B. the use of this material can provide for higher power output, improved thermal performance, and better emi margin (due to lower pcb trace resistance). 8.1.2 pvdd capacitor recommendation the large capacitors used in conjunction with each full bridge are referred to as the pvdd capacitors. these capacitors should be selected for proper voltage margin and adequate capacitance to support the power requirements. in practice, with a well-designed system power supply, 1000 f, 63-v supports more applications. the pvdd capacitors should be the low-esr type, because they are used in a circuit associated with high-speed switching. 8.1.3 decoupling capacitor recommendations to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio performance, quality decoupling capacitors should be used. in practice, x7r should be used in this application. the voltage of the decoupling capacitors should be selected in accordance with good design practices. temperature, ripple current, and voltage overshoot must be considered. this fact is particularly true in the selection of the 2.2- f capacitor that is placed on the power supply to each half-bridge. the decoupling capacitor must withstand the voltage overshoot of the pwm switching, the heat generated by the amplifier during high power output, and the ripple current created by high power output. a minimum voltage rating of 63 v is required for use with a 50-v power supply. 8.1.4 system design considerations a rising-edge transition on the reset input allows the device to execute the startup sequence and starts switching. apply audio only when the state of ready is high; that starts and stops the amplifier without having audible artifacts that are heard in the output transducers. if an overcurrent protection event is introduced, the ready signal goes low; hence, filtering is needed if the signal is intended for audio muting in non-microcontroller systems. the clip signal indicates that the output is approaching clipping. the signal can be used either to activate a volume decrease or to signal an intelligent power supply to increase the rail voltage from low to high for optimum efficiency. the device inverts the audio signal from input to output. the vreg pin is not recommended to be used as a voltage source for external circuitry. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 19 product folder links: TAS5630B
TAS5630B sles217d ? november 2010 ? revised march 2015 www.ti.com 8.2 typical application the following schematics and pcb layouts illustrate best practices used for the TAS5630B. 8.2.1 typical application schematic figure 15. typical application schematic 8.2.1.1 design requirements this device can be configured for btl, pbtl, or se mode. each mode will require a different output configuration. 8.2.1.2 detailed design procedure ? pin 1 ? overcurrent adjust resistor can be between 24 k to 68 k depending on the application. the lower resistance corresponds to the higher over-current protection level. ? pin 2 ? reset pin when asserted, it keeps outputs hi-z and no pwm switching. this pin can be controlled by a microprocessor. ? pin 3 ? start-up ramp capacitor should be 4.7 nf for btl and pbtl configurations, and 10 nf for se configuration. ? pins 4, 5, 10, 11 ? differential pair inputs ab and cd. a dc blocking capacitor of 10 f and an rc of 100 and 100 pf should be placed on each analog input. ? pin 6 ? analog comparator reference node requires close decoupling capacitor of 1 nf to ground. ? pin 7, 8, 23, 24, 57, 58 ? ground pins are connected to board ground. ? pin 9 ? regulator supply filter pin requires 0.1 uf to agnd. ? pin 12 ? frequency adjust resistor is discussed in oscillator . 20 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: TAS5630B 2 -channel h -bridge btl mode output h-bridge 2 pvdd_a, b, c, d gnd_a, b, c, d hardwire over- current limit 8 gnd vdd vreg agnd oc_adj pvdd power supply decoupling gvdd, vdd, & vreg power supply decoupling system power supplies pvdd gvdd (12v)/vdd (12v) gnd 50v 12v gnd vac bootstrap caps bst_c bst_d 2 nd order l-c output filter for each h-bridge out_c out_d gvdd_a, b, c, d bootstrap caps bst_a bst_b input_a 2 nd order l-c output filter for each h-bridge out_a out_b 8 4 output h-bridge 1 input h-bridge 1 input_b m2 m1 m3 hardwire mode control input h-bridge 2 input_c input_d vi_cm c_startup psu_ref caps for external filtering & startup/stop input dc blocking caps input dc blocking caps /reset /otw1, /otw2, /otw /clip system microcontroller or analog circuitry ready /sd analog_in_a analog_in_b analog_in_c analog_in_d freq_adj hardwire pwm frame rate adjust & master/slave mode osc_io+ osc_io- oscillator synchronization 2 2 2 2 (2)
TAS5630B www.ti.com sles217d ? november 2010 ? revised march 2015 typical application (continued) ? pin 13, 14 ? oscillator input/output. when frequency adjust pin is pulled up to vreg, the oscillator pins are configured as inputs. ? pin 15 ? shutdown pin can be monitored by a microcontroller through gpio pin. system can decide to assert reset or power down. see error reporting . ? pin 16, 17 ? there are two overtemperature warning pins for phd package. they have two different levels of warning. otw1 is lower temperature level warning than otw2. they can be monitored by a microcontroller through gpio pins. system can decide to turn on fan, lower output power or shutdown. see error reporting . ? pin 18 ? output clip indicator can be monitored by a microcontroller through a gpio pin. system can decide to lower the volume. ? pin 19 ? ready pin can be used to signal the system that the device is up and running. ? pin 20-22 ? mode pins set the input and output configurations. see table 2 for configuration setting of these pins. ? pin 25, 26, 55, 56 ? gate drive power pins provide gate voltage for half-bridges. each needs a 3.3- isolation resistor and a 0.1-uf decoupling capacitor. ? pins 27, 40, 41, 54 ? bootstrap pins for half-bridges a, b, c, d. connect 33 nf from this pin to corresponding output pins. ? pins 28, 29, 36, 37, 44, 45, 53, 54 ? output pins from half-bridges a, b, c, d. connect appropriate bootstrap capacitors to the output pins. for pwm filtering, each output mode is used with different lc configuration. ? pins 30, 31, 38, 39, 42, 43, 50, 51 ? power supply pins to half-bridges a, b, c, d. each pvdd_x has decoupling capacitor connecting to the appropriate gnd_x pin. ? pins 32, 33, 34, 35, 46, 47, 48, 49 ? connect decoupling capacitors of each power input pin to power supply ground pins. connect these pins to board ground. ? pins 59-62 ? connect ? no connect ? pins to board ground. there is no internal connection to these pins. 8.2.1.3 application curves figure 16. total harmonic + noise vs output power figure 17. output power vs supply voltage copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 21 product folder links: TAS5630B 0.005 0.01 0.1 1 10 20m 100m 1 10 100 400 p o ? output power ? w thd+n ? total harmonic distortion + noise ? % 4 w 6 w 8 w t c = 75 c g001 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 25 30 35 40 45 50 pvdd ? supply voltage ? v p o ? output power ? w 4 w 6 w 8 w t c = 75 c thd+n at 10% g001
TAS5630B sles217d ? november 2010 ? revised march 2015 www.ti.com 8.2.2 typical differential-input btl application with bd modulation filters btl output and differential input configuration is a typical audio class-d (pwm) amplifier. with differential input, the output can be configured for btl application with bd modulation. the configuration below can also be used with ad modulation. bd modulation gives better channel separation and pssr performance. figure 18. typical differential-input btl application with bd modulation filters 22 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: TAS5630B in_left_n in_left_p r_right_n in_right_p /reset /sd /otw1 /otw2 /clip ready osc_io+ osc_io- gvdd/vdd (+12v) pvdd gvdd/vdd (+12v) pvdd pvdd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vreg gnd gnd gnd gnd gnd gnd gnd vreg vreg gnd gnd gnd gnd gnd gnd gnd out_left_p out_left_m + - out_right_p out_right_m + - 17 62 63 1819 64 2021 24 23 2225 27 2629 2830 31 32 1 33 34 35 37 23 36 4 38 39 56 7 40 41 89 42 10 43 11 44 45 12 46 47 13 48 1415 49 16 50 51 52 5453 5655 57 58 59 60 61 c23 330pf c23 330pf r713.3r r713.3r c15 100pf c15 100pf r723.3r r723.3r c30100nf c30100nf c33 100nf c33 100nf c20 4.7nf c20 4.7nf c612.2uf c612.2uf r733.3r r733.3r r323.3r r323.3r c721nf c721nf r21 10k r21 10k c602.2uf c602.2uf l11 7uh l11 7uh c53 680nf c53 680nf c22100nf c22100nf r30 3.3r r30 3.3r c18 100pf c18 100pf c50 680nf c50 680nf r31 3.3r r31 3.3r c52 680nf c52 680nf c641000uf c641000uf l107uh l107uh c32 100nf c32 100nf c7710nf c7710nf c17 100pf c17 100pf c4133nf c4133nf r703.3r r703.3r c11 100pf c11 100pf c4033nf c4033nf r11 100r r11 100r l12 7uh l12 7uh r333.3r r333.3r c66 1000uf c66 1000uf c4233nf c4233nf c16 10uf c16 10uf c692.2uf c692.2uf c14 10uf c14 10uf c78 10nf c78 10nf r1947k r1947k c12 10uf c12 10uf r13100r r13100r l137uh l137uh c7410nf c7410nf c26100nf c26100nf c21 1nf c21 1nf c2510uf c2510uf c10 10uf c10 10uf c671000uf c671000uf r10100r r10100r c51 680nf c51 680nf c701nf c701nf r18100r r18100r c4333nf c4333nf c7510nf c7510nf c622.2uf c622.2uf r2022.0k r2022.0k c65 1000uf c65 1000uf c13 100pf c13 100pf c711nf c711nf c31100nf c31100nf c632.2uf c632.2uf c731nf c731nf r74 3.3r r74 3.3r r12100r r12100r c7610nf c7610nf c68 47uf63v c68 47uf63v u10 TAS5630Bphd oc_adj /reset c_startup input_a input_b vi_cm gnd agnd vreg input_c input_d freq_adj osc_io+ osc_io- /sd /otw1 /otw2 /clip ready m1 m2 m3 gnd gnd gvdd_c gvdd_d bst_d out_d out_d pvdd_d pvdd_d gnd_d gnd_a gnd_b gnd_b out_b out_b pvdd_b pvdd_b bst_b bst_c pvdd_c pvdd_c out_c out_c gnd_c gnd_c gnd_d vdd psu_ref nc nc nc nc gnd gnd gvdd_b gvdd_a bst_a out_a out_a pvdd_a pvdd_a gnd_a
TAS5630B www.ti.com sles217d ? november 2010 ? revised march 2015 8.2.3 typical differential (2n) pbtl application with bd modulation filters when there is a need for more power in an audio system, pbtl is a good choice for this application. paralleling the output after the inductors is recommended. in this configuration, the device can be driven with higher current (lower load impedance). figure 19 shows the component and pin connections. figure 19. typical differential (2n) pbtl application with bd modulation filters copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 23 product folder links: TAS5630B in_n in_p /reset /sd /otw1 /otw2 /clip ready gvdd (+12v) pvdd osc_io+ osc_io- gvdd (+12v) vdd (+12v) pvdd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vreg gnd gnd gnd gnd gnd vreg gnd gnd gnd gnd gnd gnd vreg vreg gnd gnd gnd gnd gnd gnd 12 3 4 5 6 7 89 10 11 12 13 14 15 16 1718 19 20 21 22 23 24 25 26 27 2829 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 + - out_left_p out_left_m 4.7nf 4.7nf 100nf 100nf 3.3r 3.3r 100nf 100nf 100nf 100nf 1000uf 63v 1000uf 63v 10uf 10uf 330pf 330pf 1000uf 63v 1000uf 63v 7uh 7uh 3.3r 3.3r 47k 47k 2.2uf100v 2.2uf100v 3.3r 3.3r 1nf 100v 1nf 100v 100nf 100nf 1000uf 63v 1000uf 63v 10uf 10uf 7uh 7uh 3.3r 3.3r 33nf 33nf 47uf63v 47uf63v 1uf 250v 250v 250v 1uf 250v 100r 100r 1nf 1nf 100r 100r 3.3r 3.3r 10nf100v 10nf100v 100r 100r 2.2uf100v 2.2uf100v 7uh 7uh 33nf 33nf 100nf 100nf 10nf100v 10nf100v 100pf 100pf 10uf 10uf 1nf 100v 1nf 100v TAS5630Bphd oc_adj /reset c_startup input_a input_b vi_cm gnd agnd vreg input_c input_d freq_adj osc_io+ osc_io- /sd /otw1 /otw2 /clip ready m1 m2 m3 gnd gnd gvdd_c gvdd_d bst_d out_d out_d pvdd_d pvdd_d gnd_d gnd_a gnd_b gnd_b out_b out_b pvdd_b pvdd_b bst_b bst_c pvdd_c pvdd_c out_c out_c gnd_c gnd_c gnd_d vdd psu_ref nc nc nc nc gnd gnd gvdd_b gvdd_a bst_a out_a out_a pvdd_a pvdd_a gnd_a 2.2uf100v 2.2uf100v 100pf 100pf 22.0k 22.0k 10nf100v 10nf100v 2.2uf100v 2.2uf100v 3.3r 3.3r 33nf 33nf 3.3r 3.3r 7uh 7uh 1000uf 63v 1000uf 63v 2.2uf100v 2.2uf100v 100pf 100pf 100nf 100nf 33nf 33nf 10k 10k
TAS5630B sles217d ? november 2010 ? revised march 2015 www.ti.com 8.2.4 typical se application single-ended output configuration is often used for cost effective systems. this device can be configured to drive four independent channels with four different inputs. the delivered power is not as much as btl configuration. the advantage is that the component count for four channels is the same as two btl channels. the schematic in this section shows the component and pin connections. figure 20. typical se application 24 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: TAS5630B in_b in_a in_d in_c /reset /sd /otw1 /otw2 /clip ready pvdd a pvdd b pvdd c pvdd d a b c d gvdd (+12v) pvdd osc_io+ osc_io- gvdd (+12v) vdd (+12v) pvdd pvdd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vreg gnd vreg gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vreg gnd 62 17 63 18 64 19 20 21 24 23 22 25 27 26 29 28 30 31 32 33 34 1 35 37 2 36 3 38 4 39 56 40 41 7 42 89 10 43 44 45 11 46 12 47 13 48 1415 49 16 50 51 52 54 53 56 55 57 58 59 60 61 out_b_p out_b_m + - + - out_d_p out_d_m + - out_c_p out_c_m + - out_a_p out_a_m TAS5630Bphd oc_adj /reset c_startup input_a input_b vi_cm gnd agnd vreg input_c input_d freq_adj osc_io+ osc_io- /sd /otw1 /otw2 /clip ready m1 m2 m3 gnd gnd gvdd_c gvdd_d bst_d out_d out_d pvdd_d pvdd_d gnd_d gnd_a gnd_b gnd_b out_b out_b pvdd_b pvdd_b bst_b bst_c pvdd_c pvdd_c out_c out_c gnd_c gnd_c gnd_d vdd psu_ref nc nc nc nc gnd gnd gvdd_b gvdd_a bst_a out_a out_a pvdd_a pvdd_a gnd_a 3.3r 3.3r 100nf 100nf 2.2uf 2.2uf 2.2uf 2.2uf 15uh 15uh 470uf 50v 470uf 50v 470uf 50v 470uf 50v 470uf 50v 470uf 50v 10nf 100v 10nf 100v 15uh 15uh 33nf 33nf 470uf 50v 470uf 50v 100nf100v 100nf100v 3.3r 3.3r 470uf 50v 470uf 50v 10nf 100v 10nf 100v 3.3r 3.3r 10k 1% 10k 1% 47uf63v 47uf63v 100r 100r 3.3r 3.3r 15uh 15uh 100r 100r 100nf100v 100nf100v 10uf 10uf 100pf 100pf 470nf250v 470nf250v r_comp r_comp 10k 1% 10k 1% 10uf 10uf 100nf100v 100nf100v 10uf 10uf 1nf 1nf 100nf 100nf 22.0k 22.0k 3.3r 3.3r 100nf100v 100nf100v 100pf 100pf 470uf 50v 470uf 50v 10uf 10uf 3.3r 3.3r 10uf 10uf 470nf250v 470nf250v 3.3r 3.3r 10k 10k r_comp r_comp 10k 1% 10k 1% 10nf 10nf 3.3r 3.3r 10k 10k 10nf 100v 10nf 100v 10k 1% 10k 1% 10k 1% 10k 1% 100nf 100nf 330pf 330pf 47k 47k r_comp r_comp 10k 10k r_comp r_comp 100nf100v 100nf100v 470nf250v 470nf250v 100pf 100pf 10nf 10nf 100nf100v 100nf100v 100r 100r 100nf 100nf 2.2uf 2.2uf 100r 100r 10k 10k 10k 1% 10k 1% 3.3r 3.3r 15uh 15uh 100pf 100pf 10nf100v 10nf100v 2.2uf 2.2uf 100nf100v 100nf100v 100pf 100pf 10nf100v 10nf100v 10k 1% 10k 1% 470uf 50v 470uf 50v 3.3r 3.3r 470uf 50v 470uf 50v 33nf 33nf 3.3r 3.3r 470nf250v 470nf250v 10k 10k 2.2uf 2.2uf 100nf 100nf 10k 1% 10k 1% 10nf100v 10nf100v 33nf 33nf 100nf 100nf 3.3r 3.3r 33nf 33nf 3.3r 3.3r 10nf 100v 10nf 100v 100r 100r 100nf100v 100nf100v 10nf100v 10nf100v pvdd r_comp 50v 147k 49v 165k 48v 187k <48v 191k ww w w
TAS5630B www.ti.com sles217d ? november 2010 ? revised march 2015 8.2.5 typical 2.1 system differential-input btl and unbalanced-input se application one of the attractive features of this device is that it can be configured for mixed btl and se outputs. one btl plus two se channels make up a 2.1 audio system. while the se channels are used to drive the front end and right speakers, the btl channel can deliver higher power and is used to drive a subwoofer. figure 21 shows the component and pin connections. figure 21. typical 2.1 system differential-input btl and unbalanced-input se application copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 25 product folder links: TAS5630B in_center_n in_center_p in_right in_left /reset /sd /otw1 /otw2 /clip ready gvdd (+12v) pvdd osc_io+ osc_io- gvdd (+12v) vdd (+12v) pvdd pvdd pvdd pvdd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vreg gnd vreg gnd gnd gnd gnd gnd gnd gnd vreg gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 62 17 63 18 64 1920 21 24 23 2225 27 2629 2830 31 32 33 34 1 35 37 2 36 3 38 4 39 56 40 41 7 42 89 10 43 44 45 11 46 12 47 13 48 1415 49 16 50 51 52 5453 5655 57 58 59 60 61 out_center_p out_center_m + - out_left_m out_right_m + - + - out_left_pout_right_p 100nf 100nf 100nf 100nf 10uf 10uf 10k 10k 100nf 100nf 3.3r 3.3r 10k 1% 10k 1% TAS5630Bphd oc_adj /reset c_startup input_a input_b vi_cm gnd agnd vreg input_c input_d freq_adj osc_io+ osc_io- /sd /otw1 /otw2 /clip ready m1 m2 m3 gnd gnd gvdd_c gvdd_d bst_d out_d out_d pvdd_d pvdd_d gnd_d gnd_a gnd_b gnd_b out_b out_b pvdd_b pvdd_b bst_b bst_c pvdd_c pvdd_c out_c out_c gnd_c gnd_c gnd_d vdd psu_ref nc nc nc nc gnd gnd gvdd_b gvdd_a bst_a out_a out_a pvdd_a pvdd_a gnd_a 100pf 100pf r_comp r_comp 470nf250v 470nf250v 100nf 100nf 10nf100v 10nf100v 470uf 50v 470uf 50v 100nf 100nf 10uf 10uf 1000uf 63v 1000uf 63v 100nf100v 100nf100v 100pf 100pf 100nf100v 100nf100v 330pf 330pf 10nf 100v 10nf 100v 470uf 50v 470uf 50v 10k 1% 10k 1% 10k 10k 3.3r 3.3r 47uf63v 47uf63v 3.3r 3.3r 10k 1% 10k 1% 2.2uf100v 2.2uf100v 470nf250v 470nf250v 10uf 10uf 10nf100v 10nf100v 15uh 15uh 3.3r 3.3r 680nf 250v 680nf 250v r_comp r_comp 10uf 10uf 33nf 33nf 470uf 50v 470uf 50v 3.3r 3.3r 10nf100v 10nf100v 100r 100r 10nf100v 10nf100v 1nf 100v 1nf 100v 3.3r 3.3r 100r 100r 3.3r 3.3r 47k 47k 2.2uf100v 2.2uf100v 15uh 15uh 33nf 33nf 100nf100v 100nf100v 100nf 100nf 100r 100r 3.3r 3.3r 100nf100v 100nf100v 10uf 10uf 100pf 100pf 3.3r 3.3r 100r 100r 2.2uf100v 2.2uf100v 2.2uf100v 2.2uf100v 100pf 100pf 10nf100v 10nf100v 10k 10k 10nf 100v 10nf 100v 2.2uf100v 2.2uf100v 1nf 100v 1nf 100v 680nf 250v 680nf 250v 33nf 33nf 7uh 7uh 33nf 33nf 100pf 100pf 10nf 10nf 22.0k 22.0k 100r 100r 7uh 7uh 1000uf 63v 1000uf 63v 470uf 50v 470uf 50v 3.3r 3.3r 1nf 1nf 3.3r 3.3r 10k 1% 10k 1%
TAS5630B sles217d ? november 2010 ? revised march 2015 www.ti.com 8.2.6 typical differential-input btl application with bd modulation filters, dkd package this is the same application as described in typical differential-input btl application with bd modulation filters with phd package. for dkd package an external heatsink is required to dissipate excess heat. in this package, the pcb space is not a limiting factor for dissipating excess heat. figure 22. typical differential-input btl application with bd modulation filters, dkd package 26 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: TAS5630B in_left_n in_left_p in_right_n in_right_p /sd /otw ready gvdd (+12v) pvdd osc_io+ osc_io- gvdd (+12v) vdd (+12v) pvdd pvdd /reset gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vreg gnd gnd gnd gnd gnd gnd gnd vreg gnd gnd vreg gnd gnd out_left_p out_left_m out_right_p out_right_m + - + - 12 3 4 5 6 7 89 10 11 12 13 14 15 16 17 18 19 20 21 22 33 34 35 36 37 38 39 40 41 42 43 4423 24 25 26 27 28 29 30 31 32 c88 33nf c88 33nf c85 1nf c85 1nf 3.3r 3.3r 7uh 7uh 2.2uf100v 2.2uf100v c41 33nf c41 33nf 680nf 250v 680nf 250v 10nf100v 10nf100v 3.3r 3.3r 10uf 10uf 10uf 10uf 10uf 10uf r45100r r45100r 10nf100v 10nf100v 1000uf 63v 1000uf 63v c81 100pf c81 100pf c78100pf c78100pf c37 33nf c37 33nf c79 100pf c79 100pf r1424k r1424k c35100nf c35100nf r4447k r4447k c38 100nf c38 100nf c34 2.2uf c34 2.2uf r34 1.5r r34 1.5r c80 100pf c80 100pf u12 u12 TAS5630Bdkd psu_ref vdd oc_adj /reset c_startup input_a input_b vi_cm gnd agnd vreg input_c input_d freq_adj osc_io+ osc_io- /otw out_d out_d gnd_d gnd_c out_c pvdd_c bst_c bst_b pvdd_b out_b gnd_b gnd_a out_a out_a /sd gvdd_ab bst_a pvdd_a pvdd_a m1 m2 m3 gvdd_cd bst_d pvdd_d ready pvdd_d c33 33nf c33 33nf 680nf 250v 680nf 250v c91 2.2uf c91 2.2uf 7uh 7uh r13100r r13100r c84 100nf c84 100nf 3.3r 3.3r 10nf100v 10nf100v c87 100nf c87 100nf 1nf 100v 1nf 100v 3.3r 3.3r r60100r r60100r 680nf 250v 680nf 250v 1000uf 63v 1000uf 63v 3.3r 3.3r c42100nf c42100nf c90 2.2uf c90 2.2uf r20 10k r20 10k c4410uf c4410uf 7uh 7uh 680nf 250v 680nf 250v 10uf 10uf c83 2.2uf c83 2.2uf 1000uf 63v 1000uf 63v c89 100nf c89 100nf r31 1.5r r31 1.5r 1000uf 63v 1000uf 63v c45 4.7nf c45 4.7nf 10nf100v 10nf100v c86 330pf c86 330pf 10nf100v 10nf100v 47uf63v 47uf63v r53100r r53100r 1nf 100v 1nf 100v c82 100pf c82 100pf 7uh 7uh 1nf 100v 1nf 100v 1nf 100v 1nf 100v r54100r r54100r
TAS5630B www.ti.com sles217d ? november 2010 ? revised march 2015 9 power supply recommendations absolute maximum ratings discusses most of the requirements on TAS5630B power supply. there are a few more important guidelines that should be considered. the most important parameters are the absolute maximum rating on pvdd pins, bootstrap pins and output pins. over stress the device with higher that maximum voltage rating may shorten device lifetime operation and even cause device damage. be sure that the specifications in section 6 are observed. for best audio performance, low esr bulk capacitors are recommended. depending on the application 470- f capacitor or higher should be used. as always, decoupling capacitors must be placed no more than 1 mm from the power supply pins. if pcb space is not allowed for close decoupling capacitor placement, the decoupling capacitors can be placed on the back side of the device with vias. however, it still needs to be right below the pins. 10 layout 10.1 layout guidelines use an unbroken ground plane to have a good low-impedance and -inductance return path to the power supply for power and audio signals. pcb layout, audio performance and emi are linked closely together. the circuit contains high, fast-switching currents; therefore, care must be taken to prevent damaging voltage spikes. routing of the audio input should be kept short and together with the accompanying audio-source ground. a local ground area underneath the device is important to keep solid to minimize ground bounce. it is always good practice to follow the evm layout as a guideline. netlist for this printed circuit board is generated from the schematic in figure 18 . copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 27 product folder links: TAS5630B
TAS5630B sles217d ? november 2010 ? revised march 2015 www.ti.com 10.2 layout example note t1 : pvdd bulk decoupling capacitors c60 ? c64 should be as close as possible to the pvdd_x and gnd_x pins; the heat sink sets the distance. wide traces should be routed on the top layer with direct connection to the pins and without going through vias. no vias or traces should be blocking the current path. note t2 : close decoupling of pvdd with low impedance x7r ceramic capacitors is placed under the heat sink and close to the pins. this is valid for c60, c61, c62, and c63. note t3 : heat sink must have a good connection to pcb ground. note t4 : output filter capacitors must be linear in the applied voltage range, preferably metal film types. figure 23. printed circuit board ? top layer 28 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: TAS5630B
TAS5630B www.ti.com sles217d ? november 2010 ? revised march 2015 layout example (continued) note b1 : it is important to have a direct-low impedance return path for high current back to the power supply. keep impedance low from top to bottom side of pcb through a lot of ground vias. note b2 : bootstrap low-impedance x7r ceramic capacitors placed on bottom side provide a short, low-inductance current loop. note b3 : return currents from bulk capacitors and output filter capacitors figure 24. printed circuit board ? bottom layer copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 29 product folder links: TAS5630B
TAS5630B sles217d ? november 2010 ? revised march 2015 www.ti.com 11 device and documentation support 11.1 trademarks purepath is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.2 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.3 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 30 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: TAS5630B
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TAS5630Bdkdr hssop dkd 44 500 330.0 24.4 14.7 16.4 4.0 20.0 24.0 q1 TAS5630Bphdr htqfp phd 64 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.0 q2 package materials information www.ti.com 2-oct-2014 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TAS5630Bdkdr hssop dkd 44 500 367.0 367.0 45.0 TAS5630Bphdr htqfp phd 64 1000 367.0 367.0 45.0 package materials information www.ti.com 2-oct-2014 pack materials-page 2

www.ti.com package outline c typ 14.5 13.9 42x 0.65 44x 0.38 0.25 2x 13.65 (0.28) typ 0 - 8 0.3 0.1 12.7 12.6 5.9 5.8 3.6 3.1 0.35 gage plane 1.1 0.8 a note 3 16.0 15.8 b note 4 11.1 10.9 (2.95) (0.15) exposed thermal pad powerpad ssop - 3.6 mm max height dkd0044a plastic small outline 4218846/a 07/2016 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. the exposed thermal pad is designed to be attached to an external heatsink. powerpad is a trademark of texas instruments. tm 1 44 0.12 c a b 23 22 pin 1 id area exposed thermal pad seating plane 0.1 c see detail a detail a typical scale 1.000
www.ti.com example board layout (13.2) 0.05 max around 0.05 min around 44x (2) 44x (0.45) 42x (0.65) (r0.05) typ powerpad ssop - 3.6 mm max height dkd0044a plastic small outline 4218846/a 07/2016 symm symm see details land pattern example scale:6x 1 22 23 44 tm notes: (continued) 5. publication ipc-7351 may have alternate designs. 6. solder mask tolerances between and around signal pads can vary based on board fabrication site. metal solder mask opening non solder mask defined solder mask details not to scale opening solder mask metal under solder mask solder mask defined
www.ti.com example stencil design 44x (2) 44x (0.45) 42x (0.65) (13.2) (r0.05) typ powerpad ssop - 3.6 mm max height dkd0044a plastic small outline 4218846/a 07/2016 notes: (continued) 7. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 8. board assembly site may have different recommendations for stencil design. tm solder paste example based on 0.125 mm thick stencil scale:6x symm symm 1 22 23 44
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